Low Noise Low Power Readout Circuit For Capacitance Based MEMS Accelerometers

This paper presents a low-noise low-power readout circuit for capacitance-based accelerometers, designed using a floating inverter amplifier (FIA) with chopper stabilization (CS) and correlated level shifting (CLS) techniques to correct for offset and gain error, respectively. Unlike an earlier work where the chopping amplifies the offset, in this work we do traditional chopping. The ripples are removed by a switched-capacitor notch filter and an averaging filter which can be made to be a part of the input sampling branch of a discrete-time delta-sigma modulator (DTDSM) that will eventually follow the read-out circuit. In this work, only the readout circuit without the ADC is designed in a 180 nm CMOS process, and the post-layout results show the noise floor of the readout circuit to be $0.208 \mathrm{aF} / \sqrt{\mathrm{Hz}}$ with a sensitivity of $16.67 \mathrm{mV} / \mathrm{fF}$ and a bandwidth of 1 kHz. The readout circuit does not consume any static power but the reference voltage buffer consumes $115 \mu \mathrm{~W}$ from a 1.8 V supply.