Interactive Analog IC Layout Tool with Real-time Parasitic-aware Automatic Routing Assistance

Analog routing automation is challenging compared to digital circuits due to factors such as signal cross-talk and asymmetrical ion currents caused by electromigration, which are highly correlated with physical attributes like wire length and width. Therefore, analog routing is typically performed by layout engineers instead of automation tools that are commonly used in the digital circuit design process. Equipping students or novice analog layout engineers with a robust theoretical foundation and extensive layout experience may require years of training to enable them to derive circuit layouts with superior performance. To accelerate the training process of analog layout engineers, we develop an interactive routing assistance tool. The proposed tool provides real-time parasitic-aware automatic routing suggestions guided by heuristic and cost functions based on fringe capacitance and wire length minimization for route prediction, along with an estimation of the Elmore Delay for the resulting path. This allows engineers to quickly acquire knowledge of layout design and make informed decisions. The evaluation demonstrates that the proposed tool can offer automatic routing assistance, reducing potential delay and avoiding congestion with minimal overhead.