LD-MDCT Quantization Algorithm Optimization and FPGA Realization Using DUTSQ and SFDP Techniques

In the recent audio codec standard LC3 plus, a good balance between low latency and algorithm complexity has been achieved. This standard introduces a new quantization algorithm. To reduce system resource consumption and area usage, as well as to increase operation speed, this paper implements an efficient hardware architecture for the dead-zone plus uniform threshold scalar quantization (DUTSQ) algorithm under low-latency modified discrete cosine transform (LD-MDCT), based on low-latency time-domain aliasing cancellation (LD-TDAC) technology. The proposed quantization hardware architecture, based on state machines and folded-multiplexed data paths (SFDP) technology, significantly reduces system resource consumption. Verified using Altera MAX 10 technology, the hardware architecture operates at a frequency of $75 \mathrm{MHz}_{3}$, with logical resources occupying 16% of the total resources.