Engineering ASAP7 PDK with Buried Power Rail and Backside Metal Technologies

The work presented in this paper extends ASAP7 PDK to support buried power rail and backside metal technologies. With these two technologies, more resources can be spared not only for routing internal signals of standard cells but also for routing inter-cell signals. Better chip-level routability leads to a higher core utilization and, as a result, a smaller chip area. We use this PDK to design a six-track standard cell library. Our experimental results show that we can on average reduce chip area by $13.1 \%$, worst negative slack by ${9 . 4 \%}$, total negative slack by ${4 2 \%}$, total wire length by $5.8 \%$, and via count by $19.9 \%$.