A 3-to-78-GHz Distributed Low-Noise Amplifier Incorporating High-Gain Differential $g_{\mathrm{m}}$ Cells and Balanced Active Balun in a 65-nm CMOS

This article reports an ultrawide CMOS distributed low-noise amplifier (LNA) for ultrahigh-speed communications. The proposed LNA consists of a front single-end-to-differential distributed active balun and a subsequent differential distributed amplifier (DA). Various forms of parasitic capacitance that can degrade the high-frequency performance are carefully counteracted in this scheme. The distributed active balun is based on a cascode–cascade topology with full-band mismatch compensation techniques. The differential DA is built using a neutralized cascode amplifier, merged with inductive peaking and capacitive bootstrapping. Thanks to the use of these techniques, our scheme simultaneously achieves good results in terms of gain, noise figure (NF), and balance over an ultrawide bandwidth. The LNA prototype is designed in a 65-nm CMOS technology with an area of 1.9
$\times$
0.7 mm
$^{2}$
. The LNA scores a 13.7–16.9-dB gain from 3 to 78 GHz while integrating all supply networks. The measured group delay is 45–91 ps over 3–78 GHz, and the NF is 5.5–7.8 dB up to 50 GHz. The differential outputs show a good balance of
$<$
0.37-dB gain error and
$<$
3.8
$^{\circ}$
phase error over the full bandwidth. The chip core consumes a 72-mA current from a 1.2-V supply, and the total power consumption of the chip is 170.4 mW including the consumption on the 50-
$\Omega$
load resistors.