Microprocessor Error Rate Estimation Based on IC International Standards

The main thrust of this paper is to propose a general analysis involving conducted electromagnetic interference (EMI) at the processor power bus and the occurrence of bit-flips (soft-errors) in its memory elements. At the final end, we aim at developing a procedure to predict EMI-induced bit-flips in commercial-off-the-shelf (COTS) microprocessors by means of pin-level fault injection. An in-depth experiment based on the MSP430F149-Texas Microcontroller has been carried out. For this experiment, we have inspected the embedded RAM used to store application data as well as control state variables. This RAM also serves as stack area for the control part. The EMI consequences in terms of bit-flips have been analyzed for different levels of EMI. The set of EMI levels was defined according to the International Standard Normative IEC 61000-4-29, which rules test setup and test procedures for certificating DC-low power supplied electronics with respect to conducted EMI noise throughout its power-lines. Aiming to support this work, we have developed a Std. IEC 61000-4-29 test-compliance EMI generator to inject noise into the processor power lines. The obtained results are very promising and point towards a procedure to predict conducted EMI-induced bitflips in processor memory elements.