Wafer-Scale Fabrication Technologies for Integrated Superconducting Quantum Circuits

In the upcoming decades quantum technologies, especially quantum computation, will have a strong influence on industrial, technological, economic, and social progress and are, therefore, considered to be one of the key technologies. The fundamental building blocks for quantum computation are quantum bits (qubits). The superconducting platform offers one of the most promising implementations due to its monolithic character and potential for scalability. Present research around the world primarily focusses on scaling up the number of qubits, so reliable wafer-scale fabrication technologies are mandatory. In this paper, we present our recent developments on wafer-scale fabrication of superconducting quantum circuits including Josephson junctions by the Manhattan-type technology. We discuss fabrication parameters as well as electrical characterization. For arrays out of 50 Josephson junctions with structure dimensions of 200 nm × 200 nm, we achieve a critical current standard deviation of approx. 3% on-chip and 7% on-wafer. We also show first measurement results of so fabricated transmon-type qubits with relaxation and decoherence times of T₁ = 12.5 µs and T₂ = 15.0 µs, respectively. With an increasing number of superconducting qubits and, thus, their input and read-out lines, new challenges arise: Crosstalk between qubits, unwanted modes in the qubit environment, and required interconnections. One way to counteract is the implementation of low inductance connections across coplanar waveguides. This can be realized by aluminum air bridges. In this paper we discuss the air bridges’ fabrication parameters and the impact on the integrated circuits’ elements, e.g., Josephson junctions. We show electrical and superconducting measurements with critical temperatures and critical currents of T_c > 1.0 K and I_c > 0.6 mA, respectively.