Research on Parallel Computation and Memory Optimization of Multi-Core Embedded DSP Technology in High Precision Missile Terminal Guidance Image Tracking Algorithm

This paper mainly discusses how to effectively use multi-core embedded digital signal processor (DSP) technology to realize parallel computation of image tracking algorithm and memory optimization in high precision missile terminal guidance system. With the increasing requirement of missile strike accuracy in modern war, the vision-based terminal guidance technology has been widely concerned because of its strong autonomy and anti-jamming ability. However, such image processing algorithms are usually highly computation-intensive and data dependent, which requires high real-time and hardware resources. In this paper, the key steps of image tracking algorithm are analyzed and reconstructed deeply, and the architecture suitable for parallel processing of multi-core DSP is designed by modularization. The parallel computing advantages of multi-core DSP are given full play through task division and scheduling strategies to improve the execution efficiency and real-time performance of the algorithm. Secondly, the research also focuses on memory optimization, including the design of data cache strategy, reducing data redundancy, improving memory access locality, etc., and strives to maximize the data reading speed and reduce the memory bandwidth pressure under the condition of limited embedded system resources. To sum up, this research is committed to building an efficient and stable multi-core embedded DSP environment, parallel computing model and memory optimization scheme for high-precision missile terminal guidance image tracking algorithm, which has important theoretical value and practical significance for improving the intelligence level and combat efficiency of missile terminal guidance system.