POSIT Arithmetic Hardware Implementation for Neural Network Applications

Nowadays, intense matrix multiplication is widely used in the application of Convolutional Neural Networks (CNN). Systolic Array Matrix Multiplier, a 2D pipelined array of Processing Elements (PE) beneficial for faster and more efficient computations. In addition to this, the Posit Floating Point Standard provides better precision, wider dynamic range, and improved handling of zero and infinity which can be a promising replacement for the IEEE-754 Floating Point Standard. In this paper, an efficient 5-stage pipelined architecture for Posit Adder and Posit Multiplier Arithmetic and implemented the arithmetic on a $\mathbf{4}\times \mathbf{4}$ systolic array matrix multiplier to show its efficiency and usefulness in efficient and intense matrix multiplication applications. The model is implemented using Verilog-HDL and verified on 45nm ASIC platform and Artix-7 FPGA device (xc7a35tcpg236-1). The proposed posit multiplier has 23.49% less LUT utilization. The systolic array matrix multiplier has achieved a maximum accuracy of 99.99% for the Posit (32,2) and (32,4) configurations. The proposed architecture can be applied in intense matrix multiplication for CNN applications and many other mathematical operations.