Common-Mode Voltage Reduction Technique for $1\emptyset \ \text{to}\ 6\emptyset $ Matrix Converter Using Primary-Secondary Voltage Vector Combinations

The emerging need of matrix converter (MC) is due to the existence of large dc-bus capacitors in multistage (ac–dc–ac) conversion from single-phase $( {1\emptyset } )$ to multiphase $( {m\emptyset } )$ system. The fundamental operation of MC with an appropriate voltage transfer ratio (VTR) is to maintain the supply side unity power factor. The limiting operational constraint is common-mode voltage (CMV) appearing across the load neutral and supply side return path due to discrete and impulsive converter switching. The proposed space vector modulation (SVM) approach is based on the two large voltage vectors selected as primary voltage vectors in a given sector to synthesize the reference voltage vector. From the vertically opposite plane of the selected primary voltage vectors, three voltage vectors are grouped as a secondary voltage vectors. To obtain the volt-second balance, null voltage vector activation time is distributed amongst the selected primary and secondary voltage vectors. The proposed control maintains a VTR of 0.519 in $1\emptyset {\bm{\ }}to{\bm{\ }}6\emptyset $ MC conversion while reducing the CMV up to one-third peak of the supply voltage. This proposed SVM is implemented using a low-cost digital signal processor with a laboratory prototype of $1\emptyset {\bm{\ }}to{\bm{\ }}6\emptyset {\bm{\ }}\text{MC}$ to validate the reduced CMV claim.