Open-CFR: Open-Source Co-Design Framework for Redundancy with DPR in COTS FPGA SoCs

Commercial-off-the-shelf (COTS) Field Programmable Gate Array (FPGA) systems-on-chip (SoCs) are flexible platforms combining a Processing System (PS) featuring high-performance embedded-class processors with a configurable FPGA subsystem for the deployment of hardware accelerators and ad-hoc custom peripherals. Flexibility combined with demonstrated high performance and high energy efficiency make COTS FPGA SoCs particularly attractive for space applications. One of the main challenges in using COTS FPGA SoCs in space applications is the susceptibility of the FPGA technology to Single Event Upsets (SEU) caused by ionizing particles. This paper presents Open-cfr, an Open-source Co-design Framework for redundant execution of hardware accelerators on COTS FPGA SoC platforms. From a high-level description of the target system, Open-cfr provides: (i) an automatically generated hardware shell supporting voting and detection, specifically tailored for the interface of a target hardware accelerator, (ii) a full Dynamic Partial Reconfiguration flow for fast recovery after SEU, and (iii) a generated software runtime executable for the setup and runtime management of the full redundant system. Open-cfr automates the creation of the full FPGA design, providing as output the bitstreams and software executable for the target FPGA SoC platform. We evaluate the performance of Open-cfr and compare it with state-of-the-art solutions on realistic experimental scenarios and on a use-case scenario deploying the HLS4ML framework on popular COTS FPGA SoCs from the ZYNQ family from AMD-Xilinx.