Establishment of Signal Integrity Design Rules for CMOS ICS

The benefits expected by the decreases of feature sizes in high-speed electronics circuits are limited by the increased parasitic effects of interconnect. This paper details a set of design rules extracted from experimental characterization of propagation delay and crosstalk along interconnects in deep submicron technology. A simple delay formulation is proposed, together with guidelines for choosing an interconnect model according to a given precision. The critical routing length limit over which the crosstalk effect may induce a fault is described, with emphasis on multiple crosstalk appearing in bus configurations. Finally, the cooperative research within MEDEA A-408 project concerning signal integrity is detailed.