Characterization of an EMC Test-Chip

A test-chip is developed with the aim to evaluate on-chip measures to ultimately improve the EMC behavior of ICs in their final applications. This paper describes the process of definition to obtain maximum benefit of the parameters chosen with the test-chip and some simulation results of the measures taken. Simulations show that the external decoupling has large effect, but that there's not 1 level that results in the best situation on cell, core and chip level at once. The external inductance lowers the voltage variation across the ground net of the IC whereas it increases the voltage variations of the internal cell. On-chip decoupling and grid width only shows effect for respectively the internal cell voltage and the voltage across the ground net of one core.