A Quantum Controller IC With DRAG Generation in 40-nm Cryo-CMOS for Scalable Superconducting Quantum Computing

This article presents a cryo-CMOS controller that supports derivative removal by adiabatic gate (DRAG) pulses without requiring internal memory. The proposed scheme uses trigonometric relations that substitute a product of two sinusoids by a sum of two frequencies at the same frequencies. It enables embedding the DRAG pulse shaping in an architecture of memory-free real-time direct digital synthesis (DDSs). This work also investigates the effect of inter-channel interference (ICI) and introduces a technique to suppress it by flowing compensating current to the on-chip ground. The implemented chip in 40-nm bulk CMOS supports the DRAG pulses for sine and raised-cosine shaping and suppresses the ICI by 10 dB, showing an SFDR of >40 dBc in the presence of ICI. The total power consumption when generating a rectangular pulse without DRAG is 4.2 mW, and it increases to 6.5 mW when generating sine-shaped pulse with DRAG.