HW/SW Co-Design of the Secure Hash Function SHA-256

Technological developments in data communication has increased the integration cryptographic algorithms. Hash functions are used in many security schemes such as digital signature/verification and block chain network. Secure Hash Algorithm-256 (SHA-256) is an irreversible hash function. Its algorithm is not only fast, but also provides a high security service. However, in terms of computations complexity, it requires a huge amount of arithmetic operations. This paper presents the implementation of SHA-256 core in reconfigurable FPGA circuit. Our work is based on Programmable System on Chip (PSoC) architecture. The Xilinx Microblaze processor is used for the system flexibility. The SHA-256 algorithm is composed by two steps, namely, the padding operation and the hash computation process to produce the 256-bit message digest. The proposed Hardware/Software (HW /SW) partitioning consists in the execution of the padding step in SW whereas the hash computation is implemented in HW within the SHA-256 core. The implementation results on Virtex-5 circuit show that a 512-bit message digest runs in 2.083 us. The PSoC hardware architecture requires 4058 Slices.