Hardware and Software Co-Design of FPGA-based Erasure Coding Accelerator for Enterprise Storage

In distributed storage systems, erasure coding is a well-proven and effective fault-tolerant technique that is extensively employed. The escalating demands for storage performance from enterprise users have markedly intensified the bandwidth requirements associated with erasure coding. ARM-based CPUs exhibit limitations in their performance regarding erasure coding. The use of FPGA to offload erasure coding has been covered in earlier studies. However, FPGA-based offloading schemes for erasure coding is not suitable for every storage scenario. Both performance and cost become significant challenges. To address these challenges, we propose an FPGA-based storage system acceleration architecture that enables both high performance and low cost. By constructing an EC evaluation model, a quantitative analysis mechanism is used to determine the most useful scenario. We implement a co-designed prototype of hardware and software that consists of an FPGA for erasure coding offloading and a unique software acceleration layer installed in the IEIT storage cluster. It could increase throughput by up to 2.67 times.