Punch-through variability in buried channel transistors

In this study, we present experimental findings regarding the variability observed in transistors employing a buried channel. In weak inversion regime this arsenic implantation plays the role to adjust the threshold voltage. A set of 1D simulations is used to show the impact on current-voltage characteristics. A correlation between the leakage current and the spatial position on a 300mm wafer has been considered, as well as a Principal Component Analysis. The objective is to understand the factors contributing to this variability.