Failure Analysis of VDMOS Devices in High Power Test

Power VDMOS devices are vertical double diffused structure devices and are the mainstream devices in power semiconductors today. Steady state power life test is one of the main methods to verify its ability to withstand high power for a long time. Currently, there is relatively little research on the failure of VDMOS devices in steady-state tests. This article analyse N-channel VDMOS devices that have failed after steady-state power life testing. Through investigating test conditions and equipment, static retesting, thermal impedance analysis, chip visual inspection, and other methods, the failed samples are analyzed, and the main reasons for their failure are summarized. Improvement measures have been verified to be effective. This provides reference data for subsequent analysis of related types of failures and methodological support for conducting high-power steady-state life tests on VDMOS devices.