Power Optimization of LCRC for A Custom PCI Express 6.0 IP Core

The Peripheral Component Interconnect Express (PCIe) protocol has gained extensive adoption in all computing systems. Due to the rising computational demands in edge devices, PCIe interfaces are now becoming prevalent in mobile computing systems as well. While PCIe devices employ Link-Level Cyclic Redundancy Control (LCRC) to ensure high-performance operations without compromising data integrity, this crucial feature significantly contributes to the overall power consumption. In this work, we introduce a new LCRC calculation method specifically tailored to mitigate energy usage and reduce power consumption in LCRC, offering insights into the interplay between data integrity, power consumption, and overall system performance for a custom PCIe 6.0 IP core. Our design achieves higher speeds as the CDC modules required in CRC calculation were eliminated, thus enabling relaxed timing and increased performance. Throughput per consumed energy has also been increased, improving the overall energy efficiency. Our design approach enables minimizing power consumption while maintaining the robust error-checking capabilities of the LCRC mechanism. The proposed solution establishes a balance between performance, power efficiency, and reliability in PCle-enabled devices. We have evaluated the performance of the proposed approach in terms of energy efficiency, area, and speed. In addition, we also discussed the performance implications of PCIe and high-speed parallel CRC implementations. According to the evaluation results, the overall power consumption is reduced by 38% to 85%. The proposed method in this study is universal and can be used to optimize the energy efficiency of other similar CRC calculation alaorithms in the literature.