Hardware Implementation of Projection-Aggregation Decoders for Reed-Muller Codes

This paper presents the hardware architecture and implementation of two variants of projection-aggregation-based decoding of Reed-Muller (RM) codes, namely unique projection aggregation (UPA) and collapsed projection aggregation (CPA). Through thorough analysis and experimentation, we observe that the hardware implementation of UPA exhibits superior resource usage and reduced energy consumption compared to CPA for the iterative projection aggregation (IPA) decoder. This finding underscores a critical insight: reducing computational cost, in isolation, may not necessarily translate into hardware cost effectiveness.