Comparative Analysis of 4x4 Wallace Tree Multipliers at 45nm Node Technology

In this research paper, a GDI based Wallace tree multiplier is compared with a conventional Wallace tree multiplier to analyze the power dissipation through simulation at 45nm node technology using CADENCE virtuoso design system. A GDI based Wallace tree multiplier is showing improvements in device sizing due to a smaller number of transistors, but the power dissipation is not up to expectation. This is due to more leakage as compared to the conventional design of the Wallace tree multiplier. The leakage is more because of static power dissipation, responsible for usable in high packing applications only due to less area of fabrication.