Design and Optimization of a Low Power and High-Speed Voltage Level Shifter Circuit using 45nm and 180nm MOSFETs with Variable Voltage Source

With the increasing demand for low-power and high-speed digital systems, voltage level shifters have become a critical component to enable voltage translation between different voltage domains. However, existing level shifters consume significant power and introduce delay, which can limit system performance. To address this challenge, this paper proposes a novel low-power level shifter design that achieves a voltage translation range of 0.1V to 3V, with an area of 15.84 um^2, power consumption of 171.05mW and a delay of 0.33ns. The proposed design utilizes a regulated cross-coupled pull-up network and multi-threshold voltage CMOS (MTCMOS) and sub-threshold device sizing techniques which is suitable for high-speed, low-power applications such as IoT devices, portable electronics, and integrated circuits. It achieves an optimal amalgamation of power efficiency, rapid response, and compactness. These results accentuate the efficacy of employing mixed technology nodes to enhance the performance of voltage level shifters in contemporary integrated circuits.