Design of Low Current Driver for Digital Attenuator

This paper describes a GaAs Driver logic circuit having customized gate width using WIN semi GaAs process. pHEMT E/D process is used to achieve low current consumption(1.5 mA) per bit and high speed(<10 nsec). Also E/D process is chosen as it offers ease of integration between logic functionality with RF counterpart. The circuit consist of three blocks namely Level Shifter, inverter1 and inverter2 and requires +5 V and -5 V supply for operation. The digital logic driver was integrated with a Seven-bit S-Band digital step attenuator to construct overall IC. The die is soldered over carrier using epoxy and then mounted on Rogers RO4350B peb for evaluation. The design was fabricated, tested and found to meet all design targets.