Multi-Level-Resistance Gate Driver for SiC Motor Drives to Control dv/dt and Reduce Switching Loss

Designing an optimal gate driver resistance for SiC motor drive inverters to meet the maximum dv/dt requirement is extremely critical in prolonging the motor lifetime. However, for SiC MOSFETs, turn on voltage slew rate dv/dt, decreases with increasing switching current, leading to an additional and undesirable increase in switching turn-on losses. This paper investigates how gate driver could be optimized to meet the maximum voltage slew rate through a sinusoidal load current by changing external gate resistance in limited change levels. Therefore, the switching turn-on losses under the maximum dv/dt will be significantly reduced compared to using the fixed gate driver resistance. In the proposed approach, the dynamic turn-on behaviour of SiC MOSFETs with regards to increasing miller platform voltage and decreasing dv/dt, is taken into consideration. In this paper, We theoretically demonstrate the effectiveness of the proposed multi-level resistance gate driver for SiC motor drive based on the analytical dv/dt and power loss model. The results show that by adjusting gate resistances with a few changing levels while meeting the maximum specified dv/dt requirement, turn-on switching loss can be reduced from 10 mJ to 4.5 mJ at device transconductance 12 S.