A Fully Reconfigurable Pipelined Architecture for FPGA-Based Parallel PRBS Test Pattern Generators

Serial links are widely used for data transfer in data acquisition (DAQ) systems of high-energy physics (HEP) experiments. Pseudorandom binary sequences (PRBSs) based on linear feedback shift registers (LFSRs) are commonly used as test patterns for link error testing and characterization in communication systems based on serial links. This article presents a flexible architecture for field-programmable gate array (FPGA)-based PRBS generation with full reconfigurability and high throughput. The proposed architecture is highly scalable, with extensible parallel datapaths to meet the demands of increasing data rates of serial links. The architecture is designed to be fully parametric, allowing dynamic reconfiguration of all parameters at runtime with simple writes to configuration registers. The design is optimized for efficient FPGA implementation, where extensive pipelining is exploited to achieve optimal timing performance and scalability. A built-in bootstrap unit is incorporated to generate datapath control signals from input parameters and prefill the pipeline stages on a reconfiguration event. Furthermore, a general approach to converting an existing PRBS generator into a self-synchronizing checker is illustrated and applied to the proposed architecture where an additional checker extension unit is incorporated to allow operation as a PRBS checker. The proposed flexible architecture facilitates serial link error testing with diverse test patterns, empowering the design of more robust communication systems. The architecture is implemented in chisel and verified on an Intel Agilex 7 FPGA. With the parallel output width set to 256, the design can achieve a throughput of 231.68 Gb/s with a worst case Fmax of 905 MHz.