Modeling of Through-Silicon Capacitor and Its Applications for the Optimization of Power Distribution Network in 3-D Integrated Circuits

In this article, the application of through-silicon capacitor (TSC) in the power distribution network (PDN) of three-dimensional (3-D) integrated circuits (ICs) is systematically investigated for the first time. Additionally, the deep reinforcement learning (DRL) algorithm is integrated to minimize the deployment of TSCs while achieving the target impedance, thereby reducing the cost in practical applications. By selectively replacing the specified through-silicon vias (TSV) with TSCs in the existing TSV array, this method not only ensures uniform stress distribution within the structure but also effectively reduces the required area for decoupling capacitors and enables greater flexibility in TSC applications. A comprehensive investigation is carried out to assess the electrical characteristics of TSCs and their efficiency in mitigating PDN impedance. Then, an advanced approach, combining vector fitting and neural networks, is employed for the parametric modeling of TSCs. The impedance of PDN in 3-D IC is computed using transmission matrix method. By incorporating 3-D IC PDN and TSC information as inputs, the DRL algorithm determines the optimal placement and types of TSCs. The impedance suppression effect of TSC in 3-D IC PDN is verified through various test cases, and the optimization results of DRL were compared with those of other intelligent algorithms. Finally, a comparative analysis was carried out, highlighting the significance of this article.