Josephson Latching Driver Designed Using 10-kA/cm Nb Process as Interface for Josephson-CMOS Hybrid Memory

In this study, we designed, fabricated, and experimentally tested a Josephson latching driver (JLD), a superconductor-to-semiconductor interface circuit for use in Josephson-CMOS hybrid memory, utilizing a 10-kA/cm² Nb process. The JLD is composed of a voltage driver known as a Suzuki stack and a Josephson four-junction logic (4JL) gate that serves as a preamplifier. The basic structure is based on our previous design using the 2.5-kA/cm² Nb process. In this study, we optimized the critical current and the load resistance of the 4JL gate, taking into account the parameters of the Josephson junctions in the 10-kA/cm² process. In experiments with the fabricated test circuit, we confirmed the correct operation of the JLD (bit error rate < 10⁻¹¹) at a target frequency of 5 GHz. We also confirmed the correct function of multichannel JLDs, which were used as interface circuits in Josephson-CMOS hybrid memory, in a low-frequency test.