Weight-Update Characteristics Dependent on Carrier Densities of Hf-ZnO Charge-Trap Layers in Sub-Threshold Synaptic Transistors

We present a study on a weight-update characteristics dependent on electron densities of Hf-ZnO charge-trap layers (CTLs) in a low-power synaptic thin-film transistor (Syn-TFT) operating in the sub-threshold region. For a memory function of Syn-TFTs, electrons in the Hf-ZnO CTL are de-trapped toward a channel layer with applying negative programming-pulses (PPs) to a gate terminal. Here, the Hf-ZnO CTL with a lack of electrons is insufficient to get the electron de-trapping. So, as increasing the electron density in the CTL, it is expected that the number of de-trapped electrons are also increased, which leads to a faster weight-update of the Syn-TFT compared to a lower electron density of the Hf-ZnO CTL with applying the same number of the negative PPs. Due to this phenomenon, a weight-update characteristics (i.e. a synaptic facilitation) is to be improved, which can lead to an increase of a dynamic ratio (drw) as a measure of that. To check this, the pulsed characteristics of fabricated Syn-TFTs are monitored with respect to different electron densities in the Hf-ZnO CTL. Here, the electron densities in the CTL are controlled by the growth temperature of an atomic-layer-deposition (ALD) process. From experimental results, as increasing of electron carrier densities in the Hf-ZnO CTL, it is confirmed that the weight-update of the Hf-ZnO CTL with more electron carrier density is faster than that with fewer electrons. Also, for higher carrier densities, the relaxation time is quicker through paired-pulse facilitation compared to the case of lower carrier densities.