A 1-kS/s 12-bit SAR ADC With Burst Conversion for Anti-Leakage Current

A 1-kS/s 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) which performs burst conversion is proposed to reduce the loss of the sampled analog signal due to leakage current in the capacitors of the capacitor-based digital-to-analog converter (CDAC). In order to perform burst conversion despite having a low sampling rate of 1 kHz, the proposed 12-bit SAR ADC is synchronized to 2 MHz, performing data conversion for 20 cycles and entering sleep mode for 1980 cycles to wait for the next data conversion. The capacitor-resistor DAC (CRDAC) used in the proposed SAR ADC reduces the area required for 12 bits of resolution, and the voting process allows for accurate quantization of the low 3 bits. The proposed SAR ADC is implemented using a 180-nm 1-poly six-metal CMOS process with a supply of 1.8 V. The proposed burst conversion for low-speed SAR ADCs improves the dynamic performance of ENOB from 10.82 bits to 11.59 bits for an input signal with a frequency of 450.0 Hz at a sampling rate of 1 kHz. The sleep mode operation between the burst conversions reduces the average power consumption of the SAR ADC from $47.2~\mu $ W to $9.0~\mu $ W by reducing static power consumption.