On-chip LDO with high PSRR and wide input range based on FVF architecture

A wide-input, simple-structured, fast transient response low dropout (LDO) linear regulator without output capacitor is proposed. A flipped voltage follower (FVF) structure is used to form a fast local loop that drives the power transistor, achieving fast transient response. Additionally, a cascode current mirror structure is inserted into the FVF to achieve a wide input power supply range, making it a high-voltage-tolerant structure. The power supply for the error amplifier (EA) is directly provided by the LDO output, forming a bootstrap power supply. It can operate stably within a load range of 0 to 20mA, with a quiescent current as low as 6μA. This method compensates for the shortcomings of traditional LDOs, such as low integration, large area, high power consumption, and poor transient response. The circuit is fabricated using the CSMC 180 nm process. Simulation results show that the circuit’s dropout voltage is 150 mV, the quiescent current is 6 μA, the input voltage range is 3.5-60V, and the low-frequency power supply rejection ratio (PSRR) is -150dB. When the load current changes between 0 mA and 20 mA, with an edge time of 100 ns and a load capacitance of 120 pF, the maximum overshoot generated is 60 mV, the undershoot is 70 mV, and the transient voltage recovery time is 300 ns.