3-Gsymbol/s/lane MIPI C-PHY Receiver with Feed-forward Level-dependent Equalization

A 3-Gsymbol/s/lane high-speed receiver is proposed for the mobile industry processor interface (MIPI) C-PHY. The proposed MIPI C-PHY receiver consists of high-speed receivers, level dependent elastic buffers (LDEBs), a clock recovery, and data samplers. To improve the bandwidth of level-dependent equalization using decision feedback, the proposed MIPI C-PHY receiver uses a feed-forward LDEB. The MIPI C-PHY receiver chip with three lanes was fabricated by using a 40nm CMOS process with a 1.1-V supply. The power consumption of the MIPI C-PHY receiver is 3.7 mW/Gsymbol/s/lane and the area of the receiver per lane is 400μm × 140μm. The peak-to-peak time jitter of the received data and the recovered clock measured at a symbol rate of 3 Gsymbol/s/lane is 140 ps and 92 ps, respectively.