Clock Recovery Circuit for 3-Gsymbol/s/lane MIPI C-PHY Receiver

A clock recovery circuit for use in the receive circuit of the MIPI C-PHY is proposed. The proposed clock recovery circuit removes the glitch noise that may be generated in the process of recovering the clock by detecting the edge of the received data. It performs an optimization of the control of the delay line used for the implementation of the short pulse in the conventional clock recovery circuit. To optimize this delay line, the proposed clock recovery circuit is designed by adding a clock recovery calibration circuit to the conventional clock recovery circuit, which controls the delay lines according to the pattern of data sampled by the recovered clock. The proposed clock recovery circuit supporting the MIPI C-PHY with a symbol rate of 3 GHz per lane is designed using a 65-nm CMOS process and consumes 0.2 mW during clock recovery calibration operations at a supply voltage of 1.2 V.