MRCA 2.0: An Area-Optimized Multigrained Reconfigurable Cryptographic Accelerator for Securing Blockchain-Based Internet of Things Systems

This article introduces a multigrained reconfigurable cryptographic accelerator 2.0 (MRCA 2.0), upgrading from the first 8/32/64-bit coarse-grained reconfigurable array, named MRCA, to offer high performance with a smaller area and lower power consumption for blockchain-based Internet of Things systems. To achieve these goals, we propose four innovative ideas: a dual-processing element array (D-PEA) with reduced memories, a synchronous row connection and processing element (PE) architecture, a concatenable crypto arithmetic logic unit, and heterogeneous PEs. Our MRCA 2.0 has been successfully implemented on the TySOM-3A field-programmable gate array platform across 19 different algorithms. Our application-specific integrated circuit experiment on 45-nm CMOS technology shows that MRCA 2.0 reduces area and power consumption by 1.6 and 1.4 times, respectively, compared to the previous MRCA. Compared to related works, MRCA 2.0 outperforms in throughput by 1.63–28.3 times and in energy efficiency by 1.6–3.4 times, while also offering better flexibility in supporting more 64-bit algorithms.