An Analysis and Design Guideline of High-Speed and Low-Distortion Bootstrapped Switches

Bootstrapped switches are extensively used in applications demanding high-speed and high-linearity sampling. Nevertheless, the mathematical analysis of distortions caused by parasitic effects has not been performed previously. This paper essentially analyzes three factors that affect the linearity of the switch: source-drain exchange, parasitic capacitive division, and charge redistribution. By employing the time-domain waveform integration technique along with Chebyshev polynomials, the Fourier series expression for on-resistance of the switch can be effectively elucidated. Consequently, the effects of all sources of distortion have been quantified individually. It has been found that both the on-resistance and the bootstrap capacitor has a quadratic effect (40 dB/dec) on the third-harmonic distortion of the sampled signals. A $1\times 9$ bootstrapped switch array has been fabricated using 180 nm technology to verify the proposed calculation model. Using the subsampling method, the measured total harmonic distortion (THD) performance was found to be highly consistent with the model calculation results, demonstrating the effectiveness and accuracy of the calculation model. The proposed calculation model will be highly beneficial for designers of bootstrapped switches.