Building a Model of Fault Tolerance of Serial-Parallel Ports in a Self-Synchronous Microkernel

Using redundancy at the transistor level provides optimal power consumption compared to bulk redundancy. However, due to design limitations, it is not always used in its pure form. A combined approach to redundancy maximizes the use of transistor-level registers, taking into account the decomposition of the formal output system. The power consumption of the components and devices obtained with this technology will depend on the specific circuit and given constraints and will vary between the power consumption of transistor-level registers and the power consumption of most reserves. The use of any unified base for the synthesis of self-synchronization schemes reduces the complexity of implementing the use of arbitrary elements within the framework of the used libraries, especially in schemes with memory - triggers, registers, control devices. A formal derivation system has been developed that allows using redundancy at the transistor level to obtain fault-tolerant elements from arbitrary logic elements by decomposition according to the applied rules and given constraints. A combined redundancy algorithm is developed, which allows obtaining a solution with minimal energy consumption within the given constraints. The proposed algorithm uses methods that provide passive and active fault tolerance based on the efficiency of the obtained estimate divided by the proposed formal inference system.