Tuning the parasitic JFET resistance for low on-state 1.2kV SiC power MOSFETs

This paper presents a method for extracting the channel and parasitic resistances of small pitch planar 1.2 kV SiC power MOSFETs. In addition, the influence of channel width, cell pitch and JFET doping on the overall device performance is presented. By optimizing the device design and layout, excellent static and dynamic performance is achieved. Test substrates are used for static and dynamic characterization.