SRAM With Oxide Semiconductor Pull-Down Transistors on the Backside Enabling Full-Node PPA Improvement

The 6T SRAM bitcell, consisting of four pFETs on the same tier and two oxide-semiconductor pull-down transistors stacked on the backside, can achieve 17% power reduction, 32% performance enhancement, and 42% area reduction as compared to one-tier SRAM bitcell. With the high strength ratio of the pass-gate transistors to the pull-down transistors, near-threshold-voltage write reduces the minimum operating voltage.