An Enhanced Fault Injection Framework for FPGA-Based Soft-Cores

Contemporary space system architectures necessitate rigorous validation to ensure robust performance post-deployment. Fault injection is a critical methodology that improves confidence in these systems by simulating errors under controlled conditions. Traditional fault injection approaches, such as simulation and emulation, often require costly resources or invasive alterations to the Device Under Test (DUT). The FREtZ tool addresses some of these challenges by facilitating non-invasive bit flip injections into user-bits and Configuration RAM (CRAM) bits via the FPGA's JTAG interface. However, its integration with soft-cores remains limited. This paper introduces a novel fault injection framework that extends the capabilities of the FREtZ tool. Our framework improves both the precision and the efficiency of fault injections in soft-core processors by enabling targeted fault injections at specific clock cycles or program counter locations. Hence, the injection space can be reduced to the DUT, enabling the execution of a thorough injection campaign. The proposed method not only refines the granularity of the fault injections but also streamlines the emulation process, thereby providing a more efficient and less intrusive approach to system testing. This advancement represents a significant step forward in emulation-based fault injection, particularly for complex space system architectures where reliability is paramount.