A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces

This brief presents a $10 \mathrm{~Gb} / \mathrm{s}$ low-power single-ended linear equalizer for DRAMM interfaces in 12nm FinFET technology. The proposed architecture consists of a continuous-time linear equalizer (CTLE) to compensate for the channel loss followed by a variable gain amplifier (VGA) to enhance the DC gain and sampling margin. The gain of the VGA is controlled by changing the source current, which can improve the power efficiency of the receiver based on the channel loss. Furthermore, another two common multi-stage equalizer approaches including two-stage CTLE and single-ended gain amplifier followed by a CTLE were designed and simulated in the same technology to compare with the proposed architecture. The simulation results show that the proposed linear equalizer exhibits the best overall performance in terms of power dissipation, area and eye height. The proposed equalizer consumes 0.94 mW at the Nyquist frequency of 5 GHz and 0.8 V supply voltage. It also compensates for a channel loss of 15 dB with a figure-of-merit (FoM) of $6.26 \mathrm{fJ} / \mathrm{bit} / \mathrm{dB}$, surpassing other previous works.