A Clock Duty Cycle Correction Circuitry for Ultra-Wide Frequency Range using Nested Loops

Clock duty cycle is important in high-speed interface designs, as it directly impacts the transmitted data eye width, thereby increasing the deterministic jitter (DJ) of overall high-speed link. Traditional methods of duty cycle correction (DCC) include an analog negative feedback loop, which is slow, difficult to stabilize and requires a constant clock for the loop to track and maintain the output clock’s duty cycle. Further, analog loops suffer from burst mode issues, where traffic is sporadic, and clocks are shutdown to save the power. We propose a mixed mode nested loop based digital duty cycle correction (DCC) circuitry using analog sensing loop, which overcomes the issues observed in a traditional negative feedback based analog loop. The proposed nested loop solution corrects clock duty cycle over an ultra-wide frequency range with minimal/zero power impact. The proposed solution supports duty cycle corrected clock for burst mode traffic over an ultra-wide operating frequency range. The proposed solution can find its applications in variety of clocking intellectual properties (IP) for its merits. Implemented in $7 \mathbf{n m}$ FinFET technology, the proposed nested loop based digital DCC solution achieves target duty cycle correction range requirements for $500 \mathrm{MHz}-10 \mathrm{GHz}$ frequency range with residual DC error contained within $1 \%$.