Balancing Charge Loss and Carrier Mobility: A Multiscale Modeling Approach for Device Geometry Optimization of VS-DRAM Dual-Gate Access Transistors

In the pursuit of advancing memory density, the vertically stacked dynamic random-access memory (VS-DRAM) architecture shows promise but encounters significant obstacles. This study focuses on optimizing the device geometry of VS-DRAM access transistors to achieve a delicate balance between reducing charge loss and maintaining carrier mobility. We developed a robust modeling methodology to quantify both the charge loss induced by the floating body effect (FBE) and the carrier mobility limited by surface roughness (SR). Our investigation carefully examines how thinning the transistor channel can mitigate FBE while avoiding adverse effects on surface scattering of charge carriers, all while considering the emerging geometry confinement effect. Through meticulous analysis, we aim to identify the optimal channel thickness range for VS-DRAM transistors, offering essential insights for the advancement of high-density memory technologies.