Noise Analysis of a 434-MHz Wakeup Receiver Analog Frontend Core With −93-dBm Input Sensitivity and 65-pJ/Bit Efficiency Based on a Switched Injection-Triggered Oscillator With Surface Acoustic Wave Resonator

The noise theory and measurement results of an ultralow-power receiver analog frontend core based on an switched injection-triggered oscillator (SITO) integrated in GlobalFoundries 22 nm fully depleted silicon on insulator (FD-SOI) technology are presented. Both an analytical time-domain description and a frequency-domain noise analysis for the SITO are derived. Using these, the influence of noise on the ramp-up behavior of the SITO is analyzed using a Monte Carlo simulation to predict the input sensitivity. The simulation runtime was reduced by a factor of 2400 compared with circuit simulations. An analog SITO receiver frontend with a Hartley oscillator powered from 0.5 V is designed and implemented. It achieves an input sensitivity of −93 dBm (measured, without coding) and a dc energy consumption per bit of 65 pJ/bit (measured), which improves the energy efficiency of state-of-the-art analog receiver frontends by a factor of 4.3. The measured 3 dB input filtering bandwidth is 136 kHz. The consumed dc power scales with data rate due to bitwise duty cycling from 2 nW at 10 bps up to $3.9~\mu $ W at 32 kbps (all measured), making it a perfect candidate for wakeup receivers. The noise model is validated by comparing the ramp-up time from measurements with the Monte Carlo simulation.