A 64Gb/s Si-Photonic Micro-Ring Resonator Transceiver with Co-designed CMOS Driver and TIA for WDM Optical-IO

This paper presents a hybrid-integrated Silicon Photonic (SiPh) transceiver chipsets for the in-package optical I/O. A dual-segment micro-ring modulator (MRM) and co-designed driver is proposed in the transmitter, where the main and pre-emphasis paths are separately optimized for higher aggregated bandwidth. The driver employs an asymmetric inductive peaking to compensate for MRM non-linearity. The receiver employs a cascaded ring resonator (CRR) to achieve high-Q and wide passband filtering for wavelength division multiplexing (WDM). A high-speed CMOS TIA is co-designed with integrated wavelength tuning. Polarization insensitive optical reception is achieved by the 2 D grating coupler and bidirectional input photodetector. Experimental results show the proposed SiPh transmitter achieves 3.2dB ER at $64 \mathrm{~Gb} / \mathrm{s}$ and could achieve a maximum transmission speed of $70 \mathrm{~Gb} / \mathrm{s}$. The receiver achieves 64Gb/s speed with 4.5ps RMS jitter at - 7 dBm optical input, where the $\mathbf{R X}$ bit error rate BER reaches $10^{-12}$.