Comparative Analysis of SRAM Cells with CMOS and CNTFET Technology

Rising demand for performance highlights the energy-efficient memory solutions that led to the exploration of novel materials and device technologies. CMOS-based 6T SRAM cells have long served as the cornerstone of memory designs, but recent advancements in CNTFET technology have sparked interest due to their superior electrical and mechanical properties. In this work, we evaluate the SRAM cell performance based on power dissipation, speed, area efficiency, and leakage current, across both CMOS and CNTFET platforms. Through HSPICE simulation and analysis, we evaluate the benefits and drawbacks of each technology, providing the power consumption of CNTFET-based 6T SRAM cell is $\mathbf{1 9. 2 n w}$. The read/write cycle delay for CNTFET-based SRAM cell is $473.4 \mathrm{ps} / 1.008 \mathrm{~ns}$ which is much smaller than CMOS-based SRAM cell.