Design of CAN Bus Dual Redundancy Scheme Based on FPGA

In view of the continuous expansion of the current CAN bus communication network, which brings a lot of problems such as paralysis of the communication network due to wiring failures, a dual redundancy scheme for the CAN bus based on FPGA is proposed. The aim of this paper is to make the reliability of CAN bus data transmission improved by using CAN controller redundancy technology and improving the overall integration of nodes. The system uses FPGA chip as the hardware entity carrier and integrates two self-implemented CAN controller IPs to achieve CAN bus communication. When the system is running, the two CAN channels work synchronously, and when one channel fails, it can carry out bus hot-switching in time to ensure uninterrupted operation of the system, which effectively improves the reliability of the CAN communication network.