Step-by-Step Simulation and Statistical Analysis of C and Assembly Programs for MSP430

Many low-end embedded devices, such as miniature sensors and actuators, are equipped with 8 or 16-bit microcontrollers. The computational capabilities of these microcontrollers are far below that of more powerful 32-bit processors, which is not only because of lower clock frequencies, but also due to the lack of advanced architectural and micro-architectural features like branch prediction or superscalar execution. Therefore, the quality of C compilers for these platforms is particularly crucial to achieve acceptable software performance. However, results in the recent literature show that optimizing C compilers for the 16-bit MSP430 architecture of Texas Instruments are, in terms of performance, still a lot worse (up to an order of magnitude) than hand-tuned Assembly code, even when the C sources have been carefully optimized. We present in this paper a simulation and analysis tool that can help compiler designers and software developers to spot performance deficiencies in C code. Using two cryptographic permutations, namely Ascon and Photon, as case study, we demonstrate that the tool is capable to pinpoint three shortcomings of the code-optimization backend of version 4.6.3 of MSPGCC. More concretely, we show that the produced code is sub-optimal when it comes to register allocation, the rotation of multi-word operands, and addressing modes for operations that depend heavily on static look-up tables.