Automatic Generation of Modular Multipliers Upon Pseudo-Mersenne Primes Using DSP Blocks on FPGAs

Modular multiplication is crucial and often forms the critical path in the execution of complex cryptographic algorithms such as Elliptic Curve Cryptography (ECC) and Homomorphic Encryption. Execution in ECC primarily requires multiplication and addition in $GF(p)$. On the other hand, homomorphic encryption, a cryptographic technique that allows arithmetic operations over encrypted data, requires addition and multiplication in ring $R_{q}=Z_{q}[x]/(x^{n}+1)$, which in turn requires coefficient multiplication over the integer $q$. Efforts to enhance the efficiency of modular multipliers have been extensively pursued due to the pivotal role they play in the critical path of various cryptographic operations. In recent times, FPGA boards containing DSP blocks which are capable of efficiently performing various mathematical operations stood out to be a desirable platform to design modular multipliers. But designing multipliers over FPG As stands tricky as the operand sizes supported by the DSPs are asymmetric in nature. In this paper, we propose an automated multiplier design technique that facilitates the design of modular multipliers upon pseudo-Mersenne primes. Our proposed automated multiplier design tool generates efficient hardware architectures of modular multipliers with pseudo-Mersenne primes that can be directly used in RNS (residue number system) and cryptographic algorithms like ECC in GF(p). Using the tool, we generated modular multiplier designs for various primes supporting several elliptic curves and for several RNS systems supporting a large prime. Our tool-generated hardware implementations' resource requirements regarding critical path delay and resource utilization are significantly more efficient than those of existing implementations.