An HLS Algorithm for the Direct Synthesis of Complex Control Flow Graphs Into Finite State Machines with Implicit Datapath

In this paper, we introduce an efficient algorithm for automating the direct transformation of a control flow graph (CFG) into a synthesizable finite-state machine with implicit datapath (FSMD). In our opinion, this transformation has not received sufficient attention: although the passage of a CFG to FSMD is mentioned in many textbooks on digital system design, and presented as trivial, to our knowledge it has never been explicitly formulated nor automated. Our experience shows, moreover, that this process is trickier than claimed. We believe our algorithm can become a key transformation for high-level synthesis (HLS) of control-dominated applications presenting a low level of instruction-level parallelism. Our paper presents the algorithm in detailed procedural form. Experimental measurements carried out on synthetic benchmarks shows its effectiveness.