Per-DFE Offset Measurement and Cancellation of Weighted-VREF-Based Loop-Unrolled DFE for Memory Interfaces

To achieve a high input and output (I/O) bandwidth, memory interfaces adopt a parallel I/O structure, in which the offset caused by systemic and random mismatches can limit the I/O bandwidth; thus, offset measurement and correction are required. A receiver with a loop-unrolled decision feedback equalizer (DFE) can have a per-DFE offset between two loop-unrolled data paths, degrading the overall performance. We propose an offset calibration method that can identify and adjust the per-DFE offset, thereby correcting each input-referred offset between multiple lanes. We implemented a prototype that has a two-lane receiver adopting a one-tap weighted-VREF-based DFE in a 28-nm CMOS process. Its energy efficiency and area are 0.21 pJ/bit/lane and 0.004 mm2/lane, respectively. Through the offset calibration with the DFE, a bit error rate (BER) of 10-12 and an improved eye shmoo were achieved at 12 Gb/s in a total of six data lanes in three chips.