Comparative Analysis of CPW and Slowwave CPW for Time Delay Circuit Design

In this paper, the suitability of different transmission lines for time delay circuit design is explored, focusing on Coplanar Waveguide (CPW), Grounded Coplanar Waveguide (GCPW), and two types of corresponding slow-wave structures. The performance of these structures is compared up to 40 GHz, with the aim of identifying an optimal structure that combines compact size with low insertion loss. The research is geared towards applications in millimeter-wave broadband phased array integrated circuits. Simulation results revealed that slow-wave CPW, particularly with both edge and vertical overlap parasitic capacitance loading, exhibited the highest delay per unit length and the lowest insertion loss. Subsequently, true time delay circuits were designed and implemented using this structure in a 45nm SOI process. The achieved results include a true time delay circuit with 0.4 ps delay and 0.25 dB insertion loss, and another with 3.2 ps delay and 1.3 dB insertion loss.